Tailslayer Dram Hedged Reads

If you're chasing tail latency in memory reads and DRAM refresh stalls are killing your p99s, this C++ library hedges reads across multiple DRAM channels with uncorrelated refresh schedules. You replicate data, pin workers to cores, and race all channels simultaneously so refresh on one can't block you. Built for AMD, Intel, and Graviton with undocumented channel scrambling offsets you tune via benchmarks. The API is template heavy but the pattern is clean: define a signal function that waits for your trigger, a work function that processes the value, call start_workers and let it rip. Aimed squarely at low latency trading and event driven workloads where microseconds matter.